#ifndef REG_DMAC_TYPE_H_
#define REG_DMAC_TYPE_H_
#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef struct
{
    volatile uint32_t SR;      //0x0
    volatile uint32_t CFG;           //0x4
    volatile uint32_t BPTR;          //0x8
    volatile uint32_t ALTBPTR; //0xc
    volatile uint32_t WREQSR;  //0x10
    volatile uint32_t SWREQ;         //0x14
    volatile uint32_t BSTSET;        //0x18
    volatile uint32_t BSTCLR;        //0x1c
    volatile uint32_t REQMSKSET;     //0x20
    volatile uint32_t REQMSKCLR;     //0x24
    volatile uint32_t ENSET;         //0x28
    volatile uint32_t ENCLR;         //0x2c
    volatile uint32_t PRIALTSET;     //0x30
    volatile uint32_t PRIALTCLR;     //0x34
    volatile uint32_t PRIOSET;       //0x38
    volatile uint32_t PRIOCLR;       //0x3c
    volatile uint32_t RESERVED0[3];  //0x40, 0x44, 0x48
    volatile uint32_t ERRCLR;        //0x4c
    volatile uint32_t RESERVED1[1004];
    volatile uint32_t DONERIF; // 0x1000, done interrupt flag
    volatile uint32_t ERRRIF;  // 0x1004, error interrupt flag
    volatile uint32_t RESERVED2[2];
    volatile uint32_t DONEICF; // 0x1010, done interrupt clear
    volatile uint32_t ERRICF;  // 0x1014, error interrupt clear
    volatile uint32_t DONEIEF; // 0x1018, done interrupt enable
    volatile uint32_t ERRIEF;  // 0x101c, error interrupt enable
    volatile uint32_t RESERVED3[56];
    volatile uint32_t CHSEL[2]; // 0x1100, 0x1104 channel selection configuration
} reg_dmac_t;

enum DMA_REG_SR_FIELD
{
    DMA_SR_EN_MASK = (int)0x1,
    DMA_SR_EN_POS = 0,
    DMA_SR_EN = DMA_SR_EN_MASK,
    DMA_SR_STATE_MASK = (int)0xf0,
    DMA_SR_STATE_POS = 4,
    DMA_SR_STATE = DMA_SR_STATE_MASK
};

enum DMA_REG_CFG_FIELD
{
    DMA_CFG_EN_MASK = (int)0x1,
    DMA_CFG_EN_POS = 0,
    DMA_CFG_EN = DMA_CFG_EN_MASK,
    DMA_CFG_CHNL_PROT_CTRL_MASK = (int)0xe0,
    DMA_CFG_CHNL_PROT_CTRL_POS = 5,
    DMA_CFG_CHNL_PROT_CTRL = DMA_CFG_CHNL_PROT_CTRL_MASK
};

enum DMA_REG_BPTR_FIELD
{
    DMA_BPTR_BPTR_MASK = (int)0xfffffe00,
    DMA_BPTR_BPTR_POS = 9,
    DMA_BPTR_BPTR = DMA_BPTR_BPTR_MASK
};

enum DMA_REG_ALTBPTR_FIELD
{
    DMA_ALTBPTR_ALTBPTR_MASK = (int)0xfffffe00,
    DMA_ALTBPTR_ALTBPTR_POS = 9,
    DMA_ALTBPTR_ALTBPTR = DMA_ALTBPTR_ALTBPTR_MASK
};

enum DMA_REG_WREQSR_FIELD
{
    DMA_WREQSR_WREQSR_MASK = (int)0xff,
    DMA_WREQSR_WREQSR_POS = 0,
    DMA_WREQSR_WREQSR = DMA_WREQSR_WREQSR_MASK
};

enum DMA_REG_SWREQ_FIELD
{
    DMA_SWREQ_SWREQ_MASK = (int)0xff,
    DMA_SWREQ_SWREQ_POS = 0,
    DMA_SWREQ_SWREQ = DMA_SWREQ_SWREQ_MASK,
    DMA_SWREQ_SWREQ_0 = 1 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_1 = 2 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_2 = 4 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_3 = 8 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_4 = 16 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_5 = 32 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_6 = 64 << DMA_SWREQ_SWREQ_POS,
    DMA_SWREQ_SWREQ_7 = 128 << DMA_SWREQ_SWREQ_POS
};

enum DMA_REG_BSTSET_FIELD
{
    DMA_BSTSET_BURSTSET_MASK = (int)0xff,
    DMA_BSTSET_BURSTSET_POS = 0,
    DMA_BSTSET_BURSTSET = DMA_BSTSET_BURSTSET_MASK,
    DMA_BSTSET_BURSTSET_0 = 1 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_1 = 2 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_2 = 4 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_3 = 8 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_4 = 16 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_5 = 32 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_6 = 64 << DMA_BSTSET_BURSTSET_POS,
    DMA_BSTSET_BURSTSET_7 = 128 << DMA_BSTSET_BURSTSET_POS
};

enum DMA_REG_BSTCLR_FIELD
{
    DMA_BSTCLR_BRSTCLR_MASK = (int)0xff,
    DMA_BSTCLR_BRSTCLR_POS = 0,
    DMA_BSTCLR_BRSTCLR = DMA_BSTCLR_BRSTCLR_MASK,
    DMA_BSTCLR_BRSTCLR_0 = 1 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_1 = 2 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_2 = 4 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_3 = 8 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_4 = 16 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_5 = 32 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_6 = 64 << DMA_BSTCLR_BRSTCLR_POS,
    DMA_BSTCLR_BRSTCLR_7 = 128 << DMA_BSTCLR_BRSTCLR_POS
};

enum DMA_REG_REQMSKSET_FIELD
{
    DMA_REQMSKSET_REQMSKSET_MASK = (int)0xff,
    DMA_REQMSKSET_REQMSKSET_POS = 0,
    DMA_REQMSKSET_REQMSKSET = DMA_REQMSKSET_REQMSKSET_MASK,
    DMA_REQMSKSET_REQMSKSET_0 = 1 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_1 = 2 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_2 = 4 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_3 = 8 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_4 = 16 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_5 = 32 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_6 = 64 << DMA_REQMSKSET_REQMSKSET_POS,
    DMA_REQMSKSET_REQMSKSET_7 = 128 << DMA_REQMSKSET_REQMSKSET_POS
};

enum DMA_REG_REQMSKCLR_FIELD
{
    DMA_REQMSKCLR_REQMSKCLR_MASK = (int)0xff,
    DMA_REQMSKCLR_REQMSKCLR_POS = 0,
    DMA_REQMSKCLR_REQMSKCLR = DMA_REQMSKCLR_REQMSKCLR_MASK,
    DMA_REQMSKCLR_REQMSKCLR_0 = 1 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_1 = 2 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_2 = 4 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_3 = 8 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_4 = 16 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_5 = 32 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_6 = 64 << DMA_REQMSKCLR_REQMSKCLR_POS,
    DMA_REQMSKCLR_REQMSKCLR_7 = 128 << DMA_REQMSKCLR_REQMSKCLR_POS
};

enum DMA_REG_ENSET_FIELD
{
    DMA_ENSET_CHNLEN_MASK = (int)0xff,
    DMA_ENSET_CHNLEN_POS = 0,
    DMA_ENSET_CHNLEN = DMA_ENSET_CHNLEN_MASK,
    DMA_ENSET_CHNLEN_0 = 1 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_1 = 2 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_2 = 4 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_3 = 8 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_4 = 16 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_5 = 32 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_6 = 64 << DMA_ENSET_CHNLEN_POS,
    DMA_ENSET_CHNLEN_7 = 128 << DMA_ENSET_CHNLEN_POS
};

enum DMA_REG_ENCLR_FIELD
{
    DMA_ENCLR_CHNLCLR_MASK = (int)0xff,
    DMA_ENCLR_CHNLCLR_POS = 0,
    DMA_ENCLR_CHNLCLR = DMA_ENCLR_CHNLCLR_MASK,
    DMA_ENCLR_CHNLCLR_0 = 1 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_1 = 2 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_2 = 4 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_3 = 8 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_4 = 16 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_5 = 32 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_6 = 64 << DMA_ENCLR_CHNLCLR_POS,
    DMA_ENCLR_CHNLCLR_7 = 128 << DMA_ENCLR_CHNLCLR_POS
};

enum DMA_REG_PRIALTSET_FIELD
{
    DMA_PRIALTSET_SET_MASK = (int)0xff,
    DMA_PRIALTSET_SET_POS = 0,
    DMA_PRIALTSET_SET = DMA_PRIALTSET_SET_MASK,
    DMA_PRIALTSET_SET_0 = 1 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_1 = 2 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_2 = 4 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_3 = 8 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_4 = 16 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_5 = 32 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_6 = 64 << DMA_PRIALTSET_SET_POS,
    DMA_PRIALTSET_SET_7 = 128 << DMA_PRIALTSET_SET_POS
};

enum DMA_REG_PRIALTCLR_FIELD
{
    DMA_PRIALTCLR_CLR_MASK = (int)0xff,
    DMA_PRIALTCLR_CLR_POS = 0,
    DMA_PRIALTCLR_CLR = DMA_PRIALTCLR_CLR_MASK,
    DMA_PRIALTCLR_CLR_0 = 1 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_1 = 2 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_2 = 4 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_3 = 8 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_4 = 16 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_5 = 32 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_6 = 64 << DMA_PRIALTCLR_CLR_POS,
    DMA_PRIALTCLR_CLR_7 = 128 << DMA_PRIALTCLR_CLR_POS
};

enum DMA_REG_PRIOSET_FIELD
{
    DMA_PRIOSET_SET_MASK = (int)0xff,
    DMA_PRIOSET_SET_POS = 0,
    DMA_PRIOSET_SET = DMA_PRIOSET_SET_MASK,
    DMA_PRIOSET_SET_0 = 1 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_1 = 2 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_2 = 4 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_3 = 8 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_4 = 16 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_5 = 32 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_6 = 64 << DMA_PRIOSET_SET_POS,
    DMA_PRIOSET_SET_7 = 128 << DMA_PRIOSET_SET_POS
};

enum DMA_REG_PRIOCLR_FIELD
{
    DMA_PRIOCLR_CLR_MASK = (int)0xff,
    DMA_PRIOCLR_CLR_POS = 0,
    DMA_PRIOCLR_CLR = DMA_PRIOCLR_CLR_MASK,
    DMA_PRIOCLR_CLR_0 = 1 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_1 = 2 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_2 = 4 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_3 = 8 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_4 = 16 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_5 = 32 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_6 = 64 << DMA_PRIOCLR_CLR_POS,
    DMA_PRIOCLR_CLR_7 = 128 << DMA_PRIOCLR_CLR_POS
};

enum DMA_REG_ERRCLR_FIELD
{
    DMA_ERRCLR_ERRCLR_MASK = (int)0x1,
    DMA_ERRCLR_ERRCLR_POS = 0,
    DMA_ERRCLR_ERRCLR = DMA_ERRCLR_ERRCLR_MASK
};

enum DMA_REG_RIF_FIELD
{
    DMA_RIF_DONEIF_MASK = (int)0xff,
    DMA_RIF_DONEIF_POS = 0,
    DMA_RIF_DONEIF = DMA_RIF_DONEIF_MASK,
    DMA_RIF_DONEIF_0 = 1 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_1 = 2 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_2 = 4 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_3 = 8 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_4 = 16 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_5 = 32 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_6 = 64 << DMA_RIF_DONEIF_POS,
    DMA_RIF_DONEIF_7 = 128 << DMA_RIF_DONEIF_POS
};

enum DMA_REG_ERRIF_FIELD
{
    DMA_ERRIF_ERRIF_MASK = (int)0x1,
    DMA_ERRIF_ERRIF_POS = 0,
    DMA_ERRIF_ERRIF = DMA_ERRIF_ERRIF_MASK
};

enum DMA_REG_ICF_FIELD
{
    DMA_ICF_CLR_MASK = (int)0xff,
    DMA_ICF_CLR_POS = 0,
    DMA_ICF_CLR = DMA_ICF_CLR_MASK,
    DMA_ICF_CLR_0 = 1 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_1 = 2 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_2 = 4 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_3 = 8 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_4 = 16 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_5 = 32 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_6 = 64 << DMA_ICF_CLR_POS,
    DMA_ICF_CLR_7 = 128 << DMA_ICF_CLR_POS
};

enum DMA_REG_ERRICF_FIELD
{
    DMA_ERRICF_ERRCLR_MASK = (int)0x1,
    DMA_ERRICF_ERRCLR_POS = 0,
    DMA_ERRICF_ERRCLR = DMA_ERRICF_ERRCLR_MASK
};

enum DMA_REG_IEF_FIELD
{
    DMA_IEF_SET_MASK = (int)0xff,
    DMA_IEF_SET_POS = 0,
    DMA_IEF_SET = DMA_IEF_SET_MASK,
    DMA_IEF_SET_0 = 1 << DMA_IEF_SET_POS,
    DMA_IEF_SET_1 = 2 << DMA_IEF_SET_POS,
    DMA_IEF_SET_2 = 4 << DMA_IEF_SET_POS,
    DMA_IEF_SET_3 = 8 << DMA_IEF_SET_POS,
    DMA_IEF_SET_4 = 16 << DMA_IEF_SET_POS,
    DMA_IEF_SET_5 = 32 << DMA_IEF_SET_POS,
    DMA_IEF_SET_6 = 64 << DMA_IEF_SET_POS,
    DMA_IEF_SET_7 = 128 << DMA_IEF_SET_POS
};

enum DMA_REG_ERRIEF_FIELD
{
    DMA_ERRIEF_SET_MASK = (int)0x1,
    DMA_ERRIEF_SET_POS = 0,
    DMA_ERRIEF_SET = DMA_ERRIEF_SET_MASK
};

enum DMA_REG_CHMUX1_FIELD
{
    DMA_CHMUX1_CH0SEL_MASK = (int)0x3f,
    DMA_CHMUX1_CH0SEL_POS = 0,
    DMA_CHMUX1_CH0SEL = DMA_CHMUX1_CH0SEL_MASK,
    DMA_CHMUX1_CH1SEL_MASK = (int)0x3f00,
    DMA_CHMUX1_CH1SEL_POS = 8,
    DMA_CHMUX1_CH1SEL = DMA_CHMUX1_CH1SEL_MASK,
    DMA_CHMUX1_CH2SEL_MASK = (int)0x3f0000,
    DMA_CHMUX1_CH2SEL_POS = 16,
    DMA_CHMUX1_CH2SEL = DMA_CHMUX1_CH2SEL_MASK,
    DMA_CHMUX1_CH3SEL_MASK = (int)0x3f000000,
    DMA_CHMUX1_CH3SEL_POS = 24,
    DMA_CHMUX1_CH3SEL = DMA_CHMUX1_CH3SEL_MASK
};

enum DMA_REG_CHMUX2_FIELD
{
    DMA_CHMUX2_CH4SEL_MASK = (int)0x3f,
    DMA_CHMUX2_CH4SEL_POS = 0,
    DMA_CHMUX2_CH4SEL = DMA_CHMUX2_CH4SEL_MASK,
    DMA_CHMUX2_CH5SEL_MASK = (int)0x3f00,
    DMA_CHMUX2_CH5SEL_POS = 8,
    DMA_CHMUX2_CH5SEL = DMA_CHMUX2_CH5SEL_MASK,
    DMA_CHMUX2_CH6SEL_MASK = (int)0x3f0000,
    DMA_CHMUX2_CH6SEL_POS = 16,
    DMA_CHMUX2_CH6SEL = DMA_CHMUX2_CH6SEL_MASK,
    DMA_CHMUX2_CH7SEL_MASK = (int)0x3f000000,
    DMA_CHMUX2_CH7SEL_POS = 24,
    DMA_CHMUX2_CH7SEL = DMA_CHMUX2_CH7SEL_MASK
};

#ifdef __cplusplus
}
#endif


#endif
